1. Field of the Invention
The present invention relates to an electronic circuit. More particularly, the present invention relates to a delay-locked looped (DLL) circuit for receiving an external clock signal and generating an internal clock signal.
2. Description of the Related Art
A synchronous semiconductor apparatus operates in synchronization with an external clock signal. Accordingly, a circuit for receiving the external clock signal and generating an internal clock signal having a phase that is synchronized with, or slightly leads, the phase of the external clock signal is required. A DLL circuit is usually used as such a circuit for generating an internal clock signal.
As shown in FIG. 1, a conventional DLL circuit 10 generally includes a phase comparator 12, a delay controller 14, a delay part 16 and a compensation delay part 18. The phase comparator 12 compares the phase of an external clock signal ECLK with the phase of a feedback signal FB and generates a detection signal DS corresponding to the phase difference between them. The delay controller 14 receives the detection signal DS and generates a delay control signal DCON for controlling a delay time of the delay part 16. The delay part 16 receives the external clock signal ECLK, delays the external clock signal ECLK in response to the delay control signal DCON, and generates an internal clock signal ICLK. The internal clock signal ICLK is delayed by a predetermined delay time by the compensation delay part 18 and output as the feedback signal FB. The feedback signal FB is input to the phase comparator 12 to be compared with the external clock signal ECLK. The above operation is repeated, and the DLL circuit 10 is locked when the phase of the feedback signal FB is synchronized with that of the external clock signal ECLK. Then, the internal clock signal ICLK which is completely synchronized with, or leads a little, the external clock signal ECLK, depending on the delay time set at the compensation delay part 18, is continuously generated.
In the conventional DLL circuit 10, the delay time of the delay part 16 continuously varies with the delay control signal DCON. Accordingly, the phase of the internal clock signal ICLK continuously and finely changes because a result obtained by comparing the phase of the external clock signal ECLK with that of the feedback signal FB and increasing or decreasing the delay time is usually reflected as a feedback signal FB after 1-2 clock periods. Thus, the phase of the internal clock signal ICLK continuously changes little by little even after the DLL circuit 10 is completely locked.
FIG. 2 is a graph illustrating a change in the delay control signal DCON in the conventional DLL circuit 10 of FIG. 1 when the delay control signal DCON is a digital code. The delay control signal DCON gradually increases and reaches a target. The target is the value of the delay control signal DCON in an ideal case where complete synchronization is achieved. In FIG. 2, the delay control signal DCON continuously and repeatedly increases and decreases slightly after it approaches the target. Accordingly, the phase of the internal clock signal ICLK repeatedly changes. The repetitive change in the phase results in a phase error in the internal clock signal ICLK or high frequency noise, exerting bad influence on the characteristics of the conventional DLL circuit 10.
In the typical DLL circuit 10, a low-pass filter may be added to the delay controller 14. The low-pass filter removes a high frequency component from the delay control signal DCON. In FIG. 2, a graph denoted by LDCON indicates a signal obtained by low-pass filtering the delay control signal DCON. As shown in FIG. 2, the low-pass filtered delay control signal LDCON is slower than the delay control signal DCON. Accordingly, the delay time and the phase of the internal clock signal ICLK changes more slowly. However, the delay time still continuously changes little by little.
As described above, a conventional DLL circuit has a problem in that the phase of an internal clock signal continuously changes as a delay control signal continuously changes even in a locked state.
In order to solve at least the above problem, it is a feature of an embodiment of the present invention to provide a delay-locked loop (DLL) circuit for minimizing the phase noise of an internal clock signal in a locked state.
Accordingly, in an effort to achieve the above and other features of an embodiment of the present invention there is provided a DLL circuit for receiving an external clock signal and generating an internal clock signal. In one embodiment, the DLL circuit includes a master delay loop for delaying the external clock signal by a predetermined delay time and then generating a feedback signal which is phase-synchronized with the external clock signal, and a slave stage for delaying the external clock signal by the predetermined delay time and generating the internal clock signal.
Preferably, the slave stage includes a low-pass filter for removing a high frequency component from a delay control signal used for controlling the delay time of the master delay loop and then generating a slave delay control signal, and a slave delay part for delaying the external clock signal by the delay time in response to the slave delay control signal and generating the internal clock signal.
In another embodiment, the DLL circuit includes a master delay loop for delaying the external clock signal by a predetermined first delay time and by a predetermined second delay time and generating a feedback signal which is phase-synchronized with the external clock signal, and a slave stage for delaying a signal, which is obtained by delaying the external clock signal by the predetermined first delay time, by the predetermined second delay time and generating the internal clock signal.
Preferably, the slave stage includes a low-pass filter for removing a high frequency component from a delay control signal used for controlling the predetermined second delay time of the master delay loop and generating a slave delay control signal, and a slave delay part for delaying a signal, which is obtained by delaying the external clock signal by the predetermined first delay time, by the predetermined second delay time in response to the slave delay control signal and generating the internal clock signal.
These and other features of the embodiments of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description of the preferred embodiments that follows.